Asymmetrically stressed CMOS FinFET

ABSTRACT

A CMOS device comprising a FinFET comprises at least one fin structure comprising a source region; a drain region; and a channel region comprising silicon separating the source region from the drain region. The FinFET further comprises a gate region comprising a N+ polysilicon layer on one side of the channel region and a P+ polysilicon layer on an opposite side of the channel region, thereby, partitioning the fin structure into a first side and a second side, respectively. The channel region is in mechanical tension on the first side and in mechanical compression on the second side. The FinFET may comprise any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the first side, and wherein the pFET comprises a P-channel inversion region in the second side. The CMOS device may further comprise a tensile film and a relaxed film on opposite sides of the fin structure adjacent to the source and drain regions, and an oxide cap layer over the fin structure.

BACKGROUND

1. Field of the Invention

The embodiments of the invention generally relate to complementary metal oxide semiconductor (CMOS) devices, and, more particularly, to a field effect transistor (FET) used in a CMOS device.

2. Description of the Related Art

In FET devices, hole mobility is augmented when the channel is under compression in a direction parallel to the current. Electron mobility is augmented when the channel is under tension in a direction parallel to the current. Thus, there is the complication of the need to supply oppositely stressed materials for pFETs and nFETs if the switching speed is to be optimal for both simultaneously. Conventional CMOS devices typically involve either favorably straining only pFETs or nFETs while relieving the strain on the opposite type, or be depositing separate straining films for each type of FET, which is generally costly and complicated to fabricate. Therefore, there remains a need for a novel CMOS device that has oppositely stressed materials for pFETs and nFETs.

SUMMARY

In view of the foregoing, an embodiment of the invention provides a complementary metal oxide semiconductor (CMOS) device comprising a fin field effect transistor (FinFET) comprises at least one fin structure comprising a source region; a drain region; and a channel region separating the source region from the drain region. The FinFET further comprises a gate region partitioning the fin structure into a first side and a second side, wherein the channel region is in mechanical tension on the first side of the fin structure, and wherein the channel region is in mechanical compression on the second side of the fin structure. In one embodiment, the FinFET may comprise any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the first side of the fin structure. Moreover, in another embodiment, the FinFET may comprise any of a nFET and a pFET, wherein the pFET comprises a P-channel inversion region in the second side of the fin structure. Preferably, the channel region comprises silicon. Additionally, the CMOS device may further comprise a tensile film and a relaxed film on opposite sides of the fin structure. Furthermore, the CMOS device may comprise an oxide cap layer over the fin structure.

Another aspect of the invention provides a semiconductor structure comprising at least one fin structure comprising a source region; a drain region; and a channel region connected to the source and drain regions. The semiconductor structure further includes a gate region separating the fin structure into two sides. The gate region comprises a N+ polysilicon layer adjacent to the channel region on the first side of the fin and a P+ polysilicon layer adjacent to the channel region on the opposite side of the fin (i.e., on the second side). A tensile film is adjacent to the source and drain regions on the first side of the fin structure and a relaxed film is adjacent to the source and drain regions on the second side of the fin structure. In one embodiment, the semiconductor structure further comprises FinFET comprising any of a nFET and a pFET, wherein the nFET comprises a N-channel inversion region in the first side of the fin structure. In another embodiment, the semiconductor structure further comprises a FinFET comprising any of a nFET and a pFET, wherein the pFET comprises a P-channel inversion region in the second side of the fin structure. Preferably, the channel region comprises silicon. Additionally, the semiconductor structure preferably comprises an oxide cap layer over the fin structure.

Another embodiment of the invention provides a method of forming a CMOS device comprising a FinFET, wherein the method comprises forming at least one fin structure comprising forming a source region; forming a drain region; and forming a channel region separating the source region from the drain region. The method further includes configuring a gate region over the source region and the drain region, wherein the configuring comprises partitioning the fin structure into a first side and a second side, wherein the channel region is in mechanical tension on the first side of the fin structure, and wherein the channel region is in mechanical compression on the second side of the fin structure. In one embodiment the FinFET is formed of any of a nFET and a pFET, wherein in the nFET, the method may further comprise forming a N-channel inversion region in the first side of the fin structure.

In another embodiment, the FinFET is formed of any of a nFET and a pFET, wherein in the pFET, the method may further comprise forming a P-channel inversion region in the second side of the fin structure. Preferably, the channel region comprises silicon. The method may further comprise forming a tensile film and a relaxed film on opposite sides of the fin structure. Also, the method may further comprise forming an oxide cap layer over the fin structure. Moreover, the method may further comprise forming a first film comprising nitride and having tensile stress on one side of the fin structure; releasing the tensile stress by introducing an angle implant to the first film; and forming a second film comprising nitride and having compressive stress on an opposite side of the fin structure. Alternatively, the method may further comprise forming a first film comprising nitride and having a first type of stress on the fin structure; damaging nitride on the fin structure by introducing an angle implant to the fin structure; etching the damaged nitride; and forming a second film comprising nitride and having a second type of stress on the fin structure, wherein the first type of stress is mechanically opposite to the second type of stress.

These and other aspects of embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following description, while indicating preferred embodiments of the invention and numerous specific details thereof, is given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which:

FIG. 1 illustrates a top view of a CMOS device according to an embodiment of the invention;

FIG. 2 illustrates a cross-sectional view of the CMOS device of FIG. 1 taken along line A-A′ of FIG. 1 according to an embodiment of the invention;

FIG. 3 illustrates a cross-sectional view of the CMOS device of FIG. 1 taken along line B-B′ of FIG. 1 according to an embodiment of the invention;

FIGS. 4(A) through 4(D) illustrate sequential fabrication steps for manufacturing a CMOS device according to an embodiment of the invention; and

FIG. 5 is a flow diagram illustrating a preferred method according to an embodiment of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments of the invention. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments of the invention may be practiced and to further enable those of skill in the art to practice the embodiments of the invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention.

As mentioned, there is the complication of the need to supply oppositely stressed materials for pFETs and nFETs if switching speed is to be optimal for both simultaneously. Hence, there remains a need for a novel CMOS device that has oppositely stressed materials for pFETs and nFETs. The embodiments of the invention achieve this by providing a structure and process which is the same for pFETs and for nFETs and yet provides for the correct sense of stress/strain on each simultaneously. Referring now to the drawings, and more particularly to FIGS. 1 through 5, there are shown preferred embodiments of the invention.

FIG. 1 illustrates a CMOS device 1 according to an embodiment of the invention. The CMOS device 1 includes an nFET 2 and a pFET 3 configured on the same device 1. The nFET 2 comprises a N+ source region 12 a and a N+drain region 10 a configured as fin devices of the nFET 2. Similarly, the pFET 3 comprises a P+ source region 12 b and a P+ drain region 10 b configured as fin devices of the pFET 3. For the nFET 2, each of the N+ source region 12 a and N+drain region 10 a comprises a N+ silicon layer 35 having a metal silicide sidewall layer 19 surrounding the sidewalls of the N+ silicon layer 35. In the nFET 2, adjacent to the metal silicide sidewall layers 19 is a tensile nitride film 21 on a first side of the fin and adjacent to the metal silicide sidewall layer 19 on the opposite side of the fin (i.e., on a second side) is a relaxed nitride film 23.

For the pFET 3, each of the P+ source region 12 b and P+ drain region 10 b comprises a P+ silicon layer 37 having a metal silicide sidewall layer 19 surrounding the sidewalls of the P+ silicon layer 37. In the pFET 3, adjacent to the metal silicide sidewall layers 19 on a first side of the fin is a tensile nitride film 21 and adjacent to the metal silicide sidewall layer 19 on the opposite side of the fin (i.e., on a second side) is a relaxed nitride film 23.

In the nFET 2, separating the N+ source region 12 a from the N+drain region 10 a is a channel region 13 a. Positioned at the first side of the fin in the channel region 13 a is a silicon layer 15 which is mechanically stressed such that it is in mechanical tension. Positioned at the second side of the fin in the channel region 13 a is a silicon layer 17 which is mechanically stressed such that it is in mechanical compression. A N-channel inversion region 14 is in the side in tension (i.e., on the first side of the fin). The N-channel inversion region 14 is a region within the channel region 13 a that extends from the interface at the gate dielectric layer 25 a into the channel region 13 a by approximately 1 nm. Here, a layer of electrons (not shown) that are responsible for conducting current from source 12 b to drain 10 b, forms when the gate voltage is above a threshold voltage. In the nFET 2, a gate dielectric layer 25 a is formed on one side of the channel region 13 a (i.e., on the first side of the fin) such that the gate dielectric layer 25 a is adjacent to the silicon layer 15. A gate dielectric layer 25 b is formed on the other side of the channel region 13 b (i.e., on the second side of the fin) such that the gate dielectric layer 25 b is adjacent to the silicon layer 17. The gate dielectric layers 25 a, 25 b are positioned on opposite sides of the channel region 13 a. Next, adjacent to the gate dielectric layer 25 a on the first side of the fin is a gate N+ polysilicon layer 5 and adjacent to the other gate dielectric layer 25 b on the second side of the fin is a gate P+ polysilicon layer 7. A liner material 9 such as titanium nitride (TiN) is formed adjacent to the outer wall of the N+ polysilicon layer 5 and P+ polysilicon layer 7. A gate conductor 11 preferably comprising a conducting material such as metal or N+ polysilicon is formed adjacent to the liners 9.

Similarly, in the pFET 3, separating the P+ source region 12 b from the P+drain region 10 b is a channel region 13 b. Positioned at the first side of the fin in the channel region 13 b is a silicon layer 15 which is mechanically stressed such that it is in mechanical tension. Positioned at the second side of the fin in the channel region 13 a is a silicon layer 17 which is mechanically stressed such that it is in mechanical compression. A P-channel inversion region 16 is in the side in compression (i.e., on the second side of the fin) The P-channel inversion region 16 is a region within the channel region 13 b that extends from the interface at the gate dielectric layer 25 b into the channel region 13 b by approximately 1 nm. Here, a layer of holes (not shown) that are responsible for conducting current from source 12 b to drain 10 b forms when the gate voltage is below a threshold voltage. In the pFET 3, a gate dielectric layer 25 a is formed on one side of the channel region 13 b (i.e., on the second side of the fin) such that the gate dielectric layer 25 a is adjacent to the silicon layer 17. A gate dielectric layer 25 b is formed on the other side of the channel region 13 a (i.e., on the first side of the fin) such that the gate dielectric layer 25 b is adjacent to the silicon layer 15. The gate dielectric layers 25 a, 25 b are positioned on opposite sides of the channel region 13 b. Next, adjacent to the gate dielectric layer 25 a (i.e., on the second side of the fin) is a P+ polysilicon layer 7 and adjacent to the other gate dielectric layer 25 b (i.e., on the first side of the fin) is a N+ polysilicon layer 5. A liner material 9 such as titanium nitride (TiN) is formed adjacent to the outer wall of the N+ polysilicon layer 5 and P+ polysilicon layer 7. A gate conductor 11 preferably comprising a conducting material such as metal or N+ polysilicon is formed adjacent to the liners 9.

FIG. 2 illustrates a cross-sectional view of the CMOS device 1 of FIG. 1 taken along line A-A′ (through the gate region 11) of FIG. 1 and FIG. 3 illustrates a cross-sectional view of the CMOS device 1 of FIG. 1 taken along line B-B′ (through the source regions 12 a, 12 b) of FIG. 1. As shown in FIGS. 2 and 3, the CMOS device 1 is formed on a buried oxide (BOX) layer 31 formed over a substrate 29. The fins 27 preferably comprise silicon and are capped with an oxide material 25.

FIGS. 4(A) through 4(D) illustrate sequential fabrication steps for manufacturing a CMOS device according to an embodiment of the invention. First, as shown in FIG. 4(A), a tensile nitride film 21 is formed around the fin structure 27 (and oxide cap 25). Next, an ion implant of germanium or arsenic is performed as generally denoted by the angled arrows in FIG. 4(B). Thereafter, the tensile nitride film 21 is selectively etched using well-known etching techniques as depicted in FIG. 4(C). Finally, a compressive nitride layer 33 is formed around the fin structure 27 (and oxide cap 25) and tensile nitride film 21. The sign and magnitude of the strain of the nitride film 21 is dependent on deposition details, such as the percentage of hydrogen content, pressure, and temperature of the deposition chamber. Preferably, a plasma-enhanced chemical vapor deposition (PECVD) process is employed.

The embodiments of the invention use asymmetric-work-function gates 11 on FinFET devices 2, 3 together with a process which causes the fins 27 to “bend” inward so as to put the channel 13 a, 13 b under compression on one side and under tension on the opposite side of the fin 27. In a preferred embodiment, the gate electrodes 11 are formed of N+ and P+ polysilicon and the fin 27 is strained so as to be under tension near to the N+ polysilicon layer 5 and under compression adjacent to the P+ polysilicon layer 7. Specifically, by providing for a film 21 under tension on the N+ side of the polysilicon layer 5 and the fin 27, differentially with respect to the stress in the film 21 on the opposing side, the forces upon the fin 27 result in a bending action, causing the fin 27 to slightly arch in a concave manner toward the P+ side of the polysilicon layer 7. When the fin 27 is so arched, the surface of the fin 27 on the convex side will naturally be under tension, that is, the lattice spacing of silicon atoms on the side of the channel 13 a with an N+ gate will have a physical separation slightly larger than that of unstrained silicon, while the opposite side of the fin 27 will be under compression, that is, the lattice spacing of the silicon atoms on the P+ side will be slightly less than that of unstrained silicon.

FIG. 5 (with reference to FIGS. 1 through 4(D)) is a flow diagram illustrating a method of forming a CMOS device 1 comprising a FinFET (shown collectively as nFET 2 and pFET 3), wherein the method comprises forming (101) at least one fin structure 27 comprising forming a source region 12 a, 12 b; forming a drain region 10 a, 10 b; and forming a channel region 13 a, 13 b separating the source region 12 a, 12 b from the drain region 10 a, 10 b, respectively. The method further includes configuring (103) a gate region 11 with a N+ polysilicon layer 5 adjacent one side of the channel region 13 a, 13 b and a P+ polysilicon layer 7 adjacent an opposite side of the channel region, thereby, partitioning the fin structure 27 into a first side 15 and a second side 17. As discussed above, the channel region 13 a, 13 b is in mechanical tension on the first side 15 of the fin structure 27, and the channel region 13 a, 13 b is in mechanical compression on the second side 17 of the fin structure 27.

In one embodiment the FinFET is formed of any of a nFET 2 and a pFET 3, wherein in the nFET 2, the method may further comprise forming a N-channel inversion region 14 in the first side 15 of the fin structure. In the pFET 3, the method may further comprise forming a P-channel inversion region 16 in the second side 17 of the fin structure 27. Preferably, the channel region 13 a, 13 b comprises silicon. The method may further comprise forming a tensile film 21 and a relaxed film 23 on opposite sides of the fin structure 27. Also, the method may further comprise forming an oxide cap layer 25 over the fin structure 27.

More specifically, the method may further comprise forming a first film 21 comprising nitride and having tensile stress on one side of the fin structure 27; releasing the tensile stress by introducing an angle implant to the first film 21; and forming a second film 33 comprising nitride and having compressive stress on an opposite side of the fin structure 27. Alternatively, the method may further comprise forming a first film 21 comprising nitride and having a first type of stress on the fin structure; damaging nitride on the fin structure 27 by introducing an angle implant to the fin structure 27; etching the damaged nitride; and forming a second film 33 comprising nitride and having a second type of stress on the fin structure 27, wherein the first type of stress is mechanically opposite to the second type of stress.

The several embodiments of the invention can be formed into integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments of the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments of the invention can be practiced with modification within the spirit and scope of the appended claims. 

1. A semiconductor structure comprising: at least one fin structure having a first side, a second side opposite said first side, a first end and a second end opposite said first end, said fin comprising: a source region in said first end; a drain region in said second end; and a channel region between said first end and said second end connected to said source region and said drain region; a gate region comprising an N+ polysilicon layer adjacent said channel region on said first side and a P+ polysilicon layer adjacent said channel region on said second side; a tensile film on said first side at said first end adjacent to said source region and on said first side at said second end adjacent to said drain region; and a relaxed film on said second side at said first end adjacent to said source region and on said second side at said second end adjacent to said drain region.
 2. The semiconductor structure of claim 1, all the limitations of which are incorporated herein by reference, further comprising a fin-type field effect transistor (FinFET) comprising any of a nFET and a pFET, wherein said nFET comprises a N-channel inversion region in said channel region at said first side of said fin structure.
 3. The semiconductor structure of claim 1, all the limitations of which are incorporated herein by reference, further comprising a fin-type field effect transistor (FinFET) comprising any of a nFET and a pFET, wherein said pFET comprises a P-channel inversion region in said channel region at said second side of said fin structure.
 4. The semiconductor structure of claim 1, all the limitations of which are incorporated herein by reference, further comprising a silicide layer on said first end and on said second end positioned between said first side and said tensile film and between said second side and said relaxed film.
 5. The semiconductor structure of claim 1, all the limitations of which are incorporated herein by reference, wherein said tensile film comprises a tensile nitride film and wherein said relaxed film comprises a relaxed nitride film.
 6. The semiconductor structure of claim 1, all the limitations of which are incorporated herein by reference, further comprising an oxide cap layer over said fin structure.
 7. A semiconductor structure comprising: a fin structure having a first side, a second side opposite said first side, a first end and a second end opposite said first end, said fin structure comprising a source region in said first end; a drain region in said second end; and a channel region between said first end and said second end connected to said source region and said drain region; a gate region comprising: a N+ polysilicon layer adjacent said channel region on said first side of said fin structure; and a P+ polysilicon layer adjacent said channel region on said second side of said fin structure; a tensile film on said first side at said first end adjacent to said source region and on said first side at said second end adjacent to said drain region; and a relaxed film on said second side at said first end adjacent said source region and on said second side at said second end adjacent to said drain region, wherein said tensile film is positioned on said first side at said first end and at said second end and said relaxed film is positioned on said second side at said first end and at said second end such that said fin structure is concavely arched toward said second side of said fin structure, such that at said first side of said fin structure adjacent to said N+ polysilicon layer said channel region is in tension and such that at said second side of said fin structure adjacent to said P+ polysilicon layer said channel region is in compression.
 8. The semiconductor structure of claim 1, all the limitations of which are incorporated herein by reference, wherein said channel region structurally isolates said N+ polysilicon layer on said first side of said fin structure from said P+ polysilicon layer on said second side of said fin structure.
 9. The semiconductor structure of claim 1, all the limitations of which are incorporated herein by reference, further comprising a fin-type field effect transistor (FinFET) comprising any of a nFET and a pFET, wherein said nFET comprises a N-channel inversion region in said channel region at said first side of said fin structure.
 10. The semiconductor structure of claim 7, all the limitations of which are incorporated herein by reference, further comprising a fin field effect transistor (FinFET) comprising any of a nFET and a pFET, wherein said pFET comprises a P-channel inversion region in said channel region at said second side of said fin structure.
 11. The semiconductor structure of claim 7, all the limitations of which are incorporated herein by reference, further comprising a silicide layer on said first end and on said second end positioned between said first side and said tensile film and between said second side and said relaxed film.
 12. The semiconductor structure of claim 7, all the limitations of which are incorporated herein by reference, wherein said tensile film comprises a tensile nitride film and wherein said relaxed film comprises a relaxed nitride film.
 13. The semiconductor structure of claim 7, all the limitations of which are incorporated herein by reference, further comprising an oxide cap layer over said fin structure.
 14. A semiconductor structure comprising: a n-type field effect transistor (nFET) and a p-type field effect transistor (pFET), wherein each of said nFET and said pFET comprise: at least one fin structure having a first side, a second side opposite said first side, a first end and a second end opposite said first end, said fin structure comprising a source region in said first end; a drain region in said second end; and a channel region between said first end and said second end connected to said source region and said drain region; a gate region comprising: a gate dielectric layer adjacent said channel region on said first side of said fin structure and on said second side of said fin structure; a N+ polysilicon layer on said gate dielectric layer on said first side of said fin structure; and a P+ polysilicon layer on said gate dielectric layer on said second side of said fin structure; a tensile film on said first side at said first end adjacent to said source region and on said second side at said second end adjacent to said drain region; and a relaxed film on said second side at said first end adjacent to said source region and on said second side at said second end adjacent to said drain region, wherein said tensile film is positioned on said first side at said first end and at said second end and said relaxed film is positioned on said second side at said first end and at said second end such that said fin structure is concavely arched toward said second side of said fin structure, such that at said first side adjacent said N+ polysilicon layer said channel region of said fin structure is in tension and such that adjacent said P+ polysilicon layer said channel region of said fin structure is in compression.
 15. The semiconductor structure of claim 14, all the limitations of which are incorporated herein by reference, wherein said nFET comprises a N-channel inversion region in said channel region at said first side of said fin structure.
 16. The semiconductor structure of claim 14, all the limitations of which are incorporated herein by reference, wherein said pFET comprises a P-channel inversion region in said channel region at said second side of said fin structure.
 17. The semiconductor structure of claim 14, all the limitations of which are incorporated herein by reference, further comprising a silicide layer between said first side and said tensile film and between said second side and said relaxed film.
 18. The semiconductor structure of claim 14, all the limitations of which are incorporated herein by reference, wherein said tensile film comprises a tensile nitride film and wherein said relaxed film comprises a relaxed nitride film.
 19. The semiconductor structure of claim 14, all the limitations of which are incorporated herein by reference, further comprising an oxide cap layer over said fin structure.
 20. The semiconductor structure of claim 1, all the limitations of which are incorporated herein by reference, wherein said at least one fin structure is concavely arched toward said second side of said fin structure comprising said P+ polysilicon layer. 